Sample and hold circuitry plays an important role in numerous signal processing applications. In particular, sample and hold circuitry plays a significant role in analog-to-digital converters. The typical sample and hold circuit includes a switching device, such as a transistor, and a capacitor. A time-varying input signal being sampled is periodically switched to the capacitor, thereby charging or discharging the capacitor, depending on the voltage of the signal as referenced to the voltage already across the capacitor at the time of the sample. Between each of the sampling intervals is a hold interval during which the voltage level stored on the capacitor represents the signal sample. The stored voltage level for the signal sample can then be fed to the input of an analog-to-digital converter which provides an n-bit binary number proportional to the voltage level. The n-bit binary number therefore represents an approximation of the input signal at the time of the sample.
One possible implementation of a sample and hold circuit utilizes a metal oxide semiconductor field effect transistor (MOSFET) as the switching (sampling) device. In this case, the input signal V.sub.sig to be sampled is applied to the drain of the field effect transistor and the gate is tied to the sampling signal V.sub.sample. The source of the field effect transistor is coupled to the capacitor and an output buffer. During the active state of sampling signal V.sub.sig, the MOSFET passes input signal V.sub.sig through its source/drain path to the capacitor thereby sampling signal V.sub.sig. The use of MOSFET as the switching device has significant advantages such as fabrication compatibility with complementary metal oxide semiconductor (CMOS) devices making up the associated processing circuitry. The use of the MOSFET, however, introduces the significant disadvantage of "aperture uncertainty."
With the use of the MOSFET, there are two significant sources of aperture uncertainty which occurs during transistor turn-off at the end of sampling. First, because of back-biasing effects, the threshold voltage V.sub.t of the MOSFET will vary as a function of the input signal applied to the drain. The variation in threshold voltage V.sub.t in turn changes the time at which the MOSFET turns off, thereby introducing timing errors. Second, the fall time of the sampling signal V.sub.sample is finite. Since an n channel field effect transistor will turn off when V.sub.sample -V.sub.sig =V.sub.t, and even if the variation in the threshold voltage V.sub.t due to back-biasing is discounted, the turn off time of the field effect transistor is still dependent on the time varying input signal V.sub.sig. In other words, the transistor will turn off at different times for different values of the input signal V.sub.sig. Again, timing errors are being introduced since the turn off time will be different for different values of V.sub.sig.
Thus, a need has risen for circuitry and methods for reducing aperture uncertainty in sample and hold circuits.